This application claims priority under 35 USC § 119 to Korean Patent Application No. 2007-0003414, filed on Jan. 11, 2007 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.
1. Field of the Invention
The present invention relates generally to semiconductor memory devices, and more particularly, to a data output circuit of a semiconductor memory device that properly adjusts for data from true and complementary memory cells.
2. Background of the Invention
A semiconductor memory device stores data in memory cells and outputs data stored in memory cells to an external circuit. Data may not be accurately written or read due to asymmetry of metal lines or process deviation. To reduce such inaccuracies, complementary cells as well as true cells are used in a memory array of the semiconductor memory device.
Conventionally, a complementary cell is tested by varying test patterns in a memory tester. However, the complementary cell may not be accurately tested conventionally since core architecture of the semiconductor memory device has been changed. To mitigate such problems in the conventional method, a multiplexer 10 as shown in FIG. 1 is employed such that a pair of output lines in a complementary cell path are inversely coupled with respect to a pair of output lines in a true cell path.
FIG. 1 shows a block diagram of a data output circuit in a semiconductor memory device, according to the prior art. Referring to FIG. 1, the data output circuit includes a multiplexer 10 and a sense amplifier 20. The multiplexer 10 includes a true cell path 12 and a complementary cell path 14.
The multiplexer 10 receives differential data D1 and D1B from global input/output data lines GIO and GIOB and generates selected differential data D2 and D2B to selected input/output data lines SGIO and SGIOB in response to a true cell control signal TCS and a complementary cell control signal CCS. The sense amplifier 20 senses and amplifies the selected differential data D2 and D2B to generate differential output data OUT and OUTB.
The true cell path 12 outputs a non-inverted differential data D1 as a non-inverted selected data D2 at a non-inverted data line SGIO, and outputs inverted differential data D1B as an inverted selected data D2B at an inverted data line SGIOB, in response to the true cell control signal TCS that is activated. The complementary cell path 14 outputs the non-inverted differential data D1 as the inverted selected data D2B at the inverted data line SGIOB, and outputs the inverted differential data D1B as the non-inverted selected data D2 at the non-inverted data line SGIO, in response to the complementary cell control signal CCS.
The conventional semiconductor memory device with the multiplexer 10 of FIG. 1 may test a complementary cell without variation of test patterns in a memory tester. However, the data D1 and D1B from the memory cell input to the multiplexer 10 and the data D2 and D2B output from the multiplexer 10 may not be sufficiently developed.
Currents or voltages representing the data D1, D1B, D2 and D2B may not be sufficient to be sensed. Since the true cell path 12 and the complementary cell path 14 are located at the input side of the sense amplifier 20, loading of the I/O lines SGIO and SGIOB is increased. With such increased loading, the transferred data may not be accurately sensed, and sensing speed may decrease due to mismatches between transistors and lines included in the multiple data output paths.